A hierarchical data line scheme (also referred to as a “hierarchical IO scheme”) is used as an input/output data transfer system in a memory array of a semiconductor device such as a DRAM (Dynamic Random-Access Memory). By way of example, a hierarchical data line scheme has a first data line such as a bit line, a second data line [e.g., a local input/output line (LIO line)] connected to the first data line, and a third data line [main input/output line (MIO line)] connected to the second data line. A plurality of bit lines are connected to the local input/output line (LIO line), and a plurality of local input/output lines (LIO lines) are connected to the main input/output line (MIO line) via switches.
FIG. 1 is a block diagram illustrating the general configuration of a DRAM device. It should be noted that FIG. 1 also schematically illustrates an example of a hierarchical data line structure comprising a bit line (BL), a local input/output line (LIO line) and a main input/output line (MIO line). As shown in FIG. 1, the DRAM device includes a memory array 1; an X decoder and X timing generating circuit 2; a Y decoder and Y timing generating circuit 3; a decoder control circuit 4; a DLL (Delay-Locked Loop) 9; a data latch circuit 5; an input/output interface 6; an internal clock (CLK) generating circuit 7; and a control signal generating circuit 8. The memory array 1 has banks 0 to m, and each bank has memory mats 1, 2 and 3. It goes without saying that the bank configuration and memory mat configuration within each bank are not limited to the illustrated configurations. The control signal generating circuit 8, which has a command decoder (not shown) to which a command signal [/CS (chip select), /RAS (row address strobe), /CAS (column address strobe) and /WE (write-enable)] is input, and which decodes the command, generates a control signal in accordance with the result of decoding the command and outputs the control signal to the X decoder and X timing generating circuit 2, Y decoder and Y timing generating circuit 3 and decoder control circuit 4. It should be noted that the “/” symbol preceding each signal name indicates that the signal is in the activated state when at the low level.
The row address of an input address signal (ADD) is decoded by the X decoder 2, a main word line (not shown) is activated by a main word driver (not shown), and a sub word line (SWL) is selected by a sub word driver (SWD) connected to the activated main word line. If the sub word line (SWL) attains the high level, held data is read out to the bit line (BL) from a memory cell (MC) connected to the sub word line (SWL) and the data is amplified by a sense amplifier. It should be noted that the column address of the address (ADD) is decoded by the Y decoder (column decoder) 3, the selected column select signal is activated and the bit line (BL) is connected to the local input/output line (LIO line). The data on the selected bit line (BL) is amplified by a sense amplifier, the amplified data is transferred to the local input/output line (LIO line) via a column switch, is transferred to the main input/output line (MIO line) via a switch 10 (sub amp) at the intersection of the main input/output line (MIO line) and local input/output line (LIO line), is transferred to the data latch circuit 5 and input/output interface 6 and is output externally from a DQ pin (DQ terminal). There are a plurality of the DQ pins, which are so-called multiple I/O terminals. Read data that is read out to the plurality of MIO lines is subjected to a parallel-to-serial conversion and is output serially from the DQ terminal.
When data is input externally, a data strobe signal DQS, /DQS becomes a trigger signal for latching data. A data mask signal DM is a control signal for masking data. If the data mask signal is set high at the same time that data is input, the writing of this data to a memory cell is masked (inhibited) and writing does not take place. The data mask signal DM is applied to an external terminal of the semiconductor device. There are a plurality of these terminals for data mask signals DM. Each data mask signal DM is associated with a group among a plurality of groups constituted by a corresponding plurality of DQ terminals.
In a case where data is written to a memory cell, the data mask signal DM is set low, the data is input from a DQ pin and the data is transferred from the input/output interface 6 to the data latch circuit 5. It should be noted that multiple-bit data (write data) that has been input serially from the DQ terminal is subjected to a serial-to-parallel conversion, and each item of bit data is transferred as write data to the sense amplifier of this bit line (BL) via the MIO line, intersection switch 10, LIO line and column switch of the selected bit line (BL). The sense amplifier drives the bit line (BL) in accordance with the write data, writes the data to the memory cell which is connected to this bit line (BL) and connected to the selected word line.
FIG. 2 is a diagram illustrating an example of the typical configuration of a sense amplifier. A portion of the bit line system of a shared-type sense amplifier circuit (SA) is illustrated in FIG. 2. A word line is driven by a sub word driver circuit 14. A memory cell includes an nMOS transistor including a gate electrode connected to the word line, and a drain or source connected to a bit line (BLT); and a capacitor Cs including a first end connected to the source or drain of the nMOS transistor and a second end connected to a power supply (plate electrode). Although not limited thereto, the bit line structure of FIG. 2 is assumed to be that of a folded bit line in which memory cell MC connected to sub word line SWL is connected to bit line BLT, and a memory cell connected to a neighboring sub word line (not shown) is connected to bit line BLN. A sense amplifier (SA circuit) connected across the lines of the bit line pair (BLT/BLN) includes a pMOS transistor pair including sources commonly connected to a PCS line, and cross-connected gates and drains; and an nMOS transistor pair including sources commonly connected to an NCS line, and cross-connected gates and drains. The drains of the pMOS transistor pair are connected to respective ones of the drains of the nMOS transistor pair.
In FIG. 2, the arrangement is such that bit line pair (BLT/BLN) of memory mat 0 (11) illustrated at the top of the drawing and bit line pair (BLT/BLN) of memory mat 1 (13) illustrated at the bottom of the drawing share sense amplifier (SA) 12 placed between them. A pass transistor (nMOS transistor) controlled to be conductive or non-conductive by control signal SHRB0 is provided between the sense amplifier circuit (SA circuit) and the bit line pair on the side of memory mat 0 (11), and a pass transistor (nMOS transistor) controlled to be conductive or non-conductive by control signal SHRB1 is provided between the sense amplifier (SA) and the bit line pair on the side of memory mat 1 (13). It should be noted that the terms “conductive” and “non-conductive” mean electrical operations and will have the same meaning in the description that follows.
Bit line pair BLT/BLN on the side of memory mat 0 (11) is provided with a circuit including three nMOS transistors whose gates are connected to control signal BLEQT0 so as to be controlled to be conductive or non-conductive. When these nMOS transistors are conductive, the circuit precharges bit line pair BLT/BLN from a precharge power supply and equalizes bit line pair BLT/BLN of memory mat 0 (11). It should be noted that the term “precharge” indicates initializing a succeeding operation following the end of the preceding operation and will have the same meaning in the description that follows.
Similarly, bit line pair BLT/BLN on the side of memory mat 1 (13) is provided with a circuit including three nMOS transistors whose gates are connected to control signal BLEQT1 so as to be controlled to be conductive or non-conductive. When these nMOS transistors are conductive, the circuit precharges bit line pair BLT/BLN from a precharge power supply and equalizes bit line pair BLT/BLN of memory mat 1 (13). Furthermore, connection nodes between the sense amplifier (SA circuit) and bit line pair are connected to an input/output line pair (I/O) via a column switch pair controlled to be conductive or non-conductive by high/low of column-select signal CSL. The input/output line pair (I/O) corresponds to LIO in FIG. 1 and one pair is provided in correspondence with each of memory mats 0 and 1.
A pMOS transistor 18 including a gate supplied with a control signal RSAEPIT is provided between VARY power supply line of the memory array and PCS, and an nMOS transistor 20 including a gate supplied with a control signal RSAENT is provided between VSSSA power supply line and NCS. Provided between PCS and NCS are a precharge and equalizing circuit 19 which is rendered conductive (turned on) to precharge PCS and NCS and to equalize PCS and NCS when a control signal EQCS is at a high level.
FIG. 3 is a diagram schematically illustrating the hierarchical data line structure (hierarchical IO scheme) within the memory array 1 of FIG. 1. In FIG. 3, RWBUS is a wiring for transferring data within the chip. A bus driver <k> 301 is a kth bus driver circuit connected to RWBUS. Connected to the input of bus driver <k> 301 is the output of a main data amplifier circuit (MA)<k> 302 for amplifying data on MIO lines (complementary MIOT, MION).
The input to the main data amplifier circuit (MA)<k> 302 is differentially connected to MIOT <k> and MION <k>, which are a kth MIO line pair within the array, and the output thereof is connected to a driver (BUSD) <k> 301. Write data from the RWBUS is input via a receiver 306 to a write amplifier (WA) 305, which drives MIOT <k>, MION <k>. When data is written, the write amplifier (WA) 305 receives the output from the receiver <k> 306 and outputs a differential signal to the MIO line pair MIOT <k>, MION <k>. When data is read, the main data amplifier circuit (MA) <k> 302 differentially receives signals from the MIO line pair MIOT <k> and MION <k>, converts these to a CMOS level and outputs the result to the bus driver (BUSD)<k> 301. When data is read out, the write amplifier (WA) 305 is rendered non-conductive and its output is set to a high impedance state.
Connected to the MIO line pair (MIOT <k>, MION <k>) are (m+1)-number of SWC circuits 303 (SWC <0> to SWC <m>). The SWC circuits correspond to the switches 10 at the intersections of the MIO line pairs and LIO line pairs in FIG. 1. In the example of FIG. 1, each MIO line pair is provided with SWC<0>, SWC<1> and SWC<2> in correspondence with the memory mat columns 1, 2 and 3. The SWC<0> is connected to a LIO line pair LIOT<0> and LION<0>), and the SWC<1> is connected to LIO line pair LIOT<1> and LION<1>. Similarly, the SWC<m> is connected to LIO line pair LIOT<m> and LION<m>. Selected from among the SWC<0> to SWC<m> is a SWC circuit corresponding to LIO line pairs connected to sense amplifiers SA<0>, SA<1>, • • • and SA<n> connected to a bit line of the selected memory mat. The other SWC circuits are not selected.
Although this imposes no restriction upon the invention, when data is written, SWC<i> (where i is an integer and i=0 to m holds) transfers write data on MIO line pair (MIOT<i>, MION<i>) to LIO line pair (LIOT<i>, LION<i>) via a transfer gate (also referred to as a “pass transistor”) (not shown). When data is read, SWC<i> receives, at a sub-amplifier (read amplifier) (not shown), read data, which has been transferred from the LIO line pair (LIOT<i>, LION<i>), from the sense amplifier of the selected bit line, and outputs the data to the MIO line pair (MIOT<i>, MION<i>). The LIO line pair has its connection to (n+1)-number sense amplifiers SA<0> to SA<n> controlled by (n+1)-number of column-select signals CSL<0> to CSL<n>, and the selected one sense amplifier SA is connected to the LIO line pair.
As an example of a semiconductor storage device including the above-described hierarchical data line structure, Patent Document 1 discloses an arrangement in which an amplifier for reading is provided between a segment data line pair and a global data line pair in a hierarchical bus, with a transfer gate for writing being provided elsewhere. The transfer gate is controlled to be electrically conductive only when data is written.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-07-334985 and U.S. Pat. No. 5,657,286A